1. Field of the Invention
The present invention relates to a method for fabricating a flash memory device, and more particularly to a method for forming metal interconnections for a flash memory device, in which a damascene process is used such that the photoresist margin can be ensured and the capacitance between the metal interconnections can be reduced.
2. Description of the Prior Art
In a 0.115 μm flash memory device being currently developed, the linewidth and space between metal interconnections have very small values of 0.135 μm and 0.135 μm, respectively, and thus, a damascene process is generally used to form the metal interconnections. However, due to a small thickness of a photoresist film, the margin of etch selectivity becomes insufficient, so that the space between the metal interconnections (i.e., the thickness of an insulating film) will be significantly reduced to increase the capacitance between the metal interconnections, thereby causing RC delay at a serious level.
In an attempt to solve this problem, there is a developed method wherein dual damascene trenches are formed, and before depositing a tungsten metal film in the trench structure, a barrier film is deposited on the trench structure to prevent loss of the underlying oxide film during a subsequent wet cleaning step.
Hereinafter, the prior method for forming metal interconnections for a flash memory device will be described with reference to FIGS. 1A to 1C.
FIGS. 1A to 1C are cross-sectional views for illustrating a method for metal interconnections for a flash memory device according to the prior art.
As shown in FIG. 1A, a device isolation film (not shown) is formed on a P-type semiconductor substrate 1 having a cell region and a peripheral region by a shallow trench isolation (STI) process. Then, an ion implantation process is performed to form a N-well and a P-well in the substrate. Alternatively, the N-well and the P-well may be first formed before forming the device isolation film.
Then, PMOS and NMOS gates are formed on the substrate including the N- and P-wells while interposing a gate insulating film 2 therebetween. Each of the formed PMOS and NMOS gates consists of a floating gate 3, a dielectric film 4 and a control gate 5, which are sequentially deposited. The control gate 5 has a three-layered structure consisting of a polycrystalline silicon film, a tungsten silicide film and a silicon nitride film for hard masks.
Subsequently, insulating spacers 6 are formed at both sides of each of the gates. At this time, although not shown, a source and a drain are formed below both sides of each of the gates, respectively.
Next, the NMOS gate in the peripheral region is partially etched. Namely, the control gate 5 and the dielectric film 4 of the NMOS gate are partially etched to form a first contact hole (not shown) exposing the floating gate 3. Then, a silicon nitride film 7 is formed on the entire surface of the substrate including the first contact hole. The silicon nitride film 7 acts to prevent loss of a first oxide film during a subsequent wet cleaning step. Furthermore, the silicon nitride film 7 is formed in the form of a spacer in such a manner that it covers the inner surface of the first contact hole in the NMOS gate of the peripheral region.
Then, a first oxide film 9 is formed on the entire surface of the resulting substrate, and selectively etched to form a second contact hole 10 exposing the source of the cell region. In etching the first oxide film 9, the silicon nitride film 7 is used as an etch stopper.
Subsequently, a first polycrystalline silicon film (not shown) is deposited on the entire surface of the substrate including the second contact hole 10, and etched back to form a first plug 12 filling the second contact hole 10.
Then, a second oxide film 14 is formed on the entire surface including the first plug 12, and selectively etched to form a third contact hole 15 exposing the drain of the cell region. Thereafter, a second polycrystalline film (not shown) is deposited on the entire surface of the substrate including the third contact hole 15, and etched back to form a second plug 16 filling the third contact hole 15.
Next, as shown in FIG. 1B, a third oxide film 18 is formed on the substrate including the second plug 16, and selectively etched to form dual damascene trenches which expose the first and second plugs 12 and 13 of the cell region, and portions of the second oxide films corresponding to the source and drain of the peripheral region (i.e., the PMOS and NMOS active regions of the peripheral region) and to the first contact hole, respectively. Then, using the dual damascene trench structure of the third oxide film as a mask, the first oxide film and the first oxide film are etched to form fourth contact holes 19 which expose the first and second plugs 12 and 16 of the cell region, the source and drain of the peripheral region, and the first contact hole of the peripheral region, respectively.
Thereafter, as shown in FIG. 1C, a metal film (not shown) made of a material such as tungsten is deposited on the entire surface of the substrate including the fourth contact holes 19, and then subjected to chemical mechanical polishing (CMP) to form metal interconnections 22 filling the fourth contact holes 19. In FIG. 1C, the reference numeral 20 denotes a barrier film interposed between the fourth contact holes 19 and the metal interconnections 22.
FIG. 2 is a partial cross-sectional view of the peripheral region in FIG. 1b, which illustrates problems occurring in the prior method.
Referring to FIG. 2, when forming the barrier film according to the prior method, the silicon nitride film of a spacer form remains on the inner surface of the first contact hole in the NMOS gate of the peripheral region (see portion A in FIG. 2). Thus, the contact area to the control gate is reduced, resulting in an increase in contact resistance.
Meanwhile, in forming the metal interconnections, if the fourth contact holes for forming the metal interconnections are formed at the stepped portion of the third oxide film, the exposure margin will be insufficient, and also the photoresist margin will be insufficient since etching must be performed in such a manner as to expose the source and drain of the peripheral region. For this reason, the prior method has a problem in that contact patterns (fourth contact holes) are not properly formed such that the fourth contact holes are not properly opened.